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AN4803
Application note
High-speed SI simulations using IBIS and board-level simulations
using HyperLynx SI on STM32 32-bit ARM® Cortex® MCUs
Introduction
This application note serves as a guide on how to use the IBIS (I/O Buffer Information
Specification) models of STMicroelectronics STM32 32-bit ARM® Cortex® MCUs and it is
also a guide in how to use the external peripherals to perform board-level simulations with
the HyperLynx® SI (Signal Integrity) software to address SI issues.
In order to use a concrete case, this application uses STM32F7xx Series as an example
due to its complexity. All the information and conclusions can be extrapolated to all the
STM32 32-bit ARM® Cortex® MCUs.
The STM32F7xx Series is based on ARM® Cortex®-M7 with FPU (floating point unit)
processor. It is the latest generation of ARM® processors for embedded systems. It was
developed to provide a low-cost platform that meets the needs of a MCU implementation.
They have a reduced pin count and perform a low-power consumption while delivering an
outstanding computational performance and a low-interrupt latency.
The STM32F7xx has a frequency of up to 216 MHz and a system speed of up to 100 MHz
when interfacing with a high-speed interface such as SDRAM (Synchronous Dynamic
Random-Access Memory).
As the signal speed increases it creates SI and EMC (Electro Magnetic Compliance) issues.
It could be detected via test equipments as a signal degradation: overshooting,
undershooting, ringing, crosstalk or timing delay. The signal degradation could be caused by
a board design failure on certification (CE/FCC) or by timing violation issues between the IC
(Integrated Circuit) drivers and the receiver. The accent should be put on getting the designs
right the first time, avoiding costly over design, and saving recurrent layouts and prototypes.
Therefore, performing a SI simulation is very important before doing any prototype.
April 2016
DocID028793 Rev 1
1/25
www.st.com
1
List of tables
AN4803
List of tables
Table 1.
Table 2.
2/25
I/Os in/output buffer for "io8p_arsudq_ft" selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DocID028793 Rev 1
AN4803
Contents
Contents
1
SI fundamentals and STM32 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
2
3
Signal integrity fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.1
Signal integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.2
Transmission line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.3
Transmission line model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.4
Characteristic impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IBIS model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.1
IC modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.2
Basic structure of an IBIS file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM32 IBIS model selection/selector . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
GPIO structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Model selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Example of model selector on STM32F7xx MCU . . . . . . . . . . . . . . . . . . 10
Application example with HyperLynx simulator . . . . . . . . . . . . . . . . . 12
3.1
3.2
HyperLynx simulation with SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1
SDRAM signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2
SDRAM simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
HyperLynx simulation with Quad-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1
Quad-SPI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2
Quad-SPI simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DocID028793 Rev 1
3/25
3
List of figures
AN4803
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.